----------------------------------------------------------------------------------
-- INSTITUTION:    Xidian University
-- DESIGNER:       Yuan Xiaoguang & Ren Aifeng    
-- 
-- Create Date:    16:53:58 02-14-2016 
-- Design Name:    TIMER_TOP 
-- Module Name:    TIMER_TOP
-- Project Name:   Timer
-- Target Devices: EP3C16F484C6
-- Tool versions:  Quartus II 13.1
-- Design Lauguage:VHDL
-- Dependencies:   -
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: DE0 Board Input Freguency = 50 MHz
--                      Destiny Output  Freguency =  1 Hz
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity TIMER_TOP is
	port(
		i_sys_clk: in STD_LOGIC;
		i_sys_rst: in STD_LOGIC;	
		o_sec0_display: out STD_LOGIC_VECTOR(6 downto 0);
		o_sec1_display: out STD_LOGIC_VECTOR(6 downto 0);
		o_min0_display: out STD_LOGIC_VECTOR(6 downto 0);
		o_min1_display: out STD_LOGIC_VECTOR(6 downto 0)
	);
end entity TIMER_TOP;

architecture behavior of TIMER_TOP is
	component FREQUENCY_DIVIDER is
	generic(
		sys_clk_fre_value: INTEGER := 50000000;
		div_clk_fre_value: INTEGER := 1
	);
	port(
		i_sys_clk: in STD_LOGIC;
		i_sys_rst: in STD_LOGIC;	
		o_div_clk: out STD_LOGIC	
	);
	end component;
	component BCD_COUNTER is
	generic(
		mod_value: INTEGER
	);
	port(
		i_sys_clk: in STD_LOGIC;
		i_sys_rst: in STD_LOGIC;
		i_count_carry_in: in STD_LOGIC;
		o_count: out STD_LOGIC_VECTOR (3 downto 0);	
		o_count_carry_out: out STD_LOGIC
	);
	end component;
	component SEG_CONVERTER is
	port(
		i_time_val: in STD_LOGIC_VECTOR (3 downto 0);
		i_sys_rst: in STD_LOGIC;	
		o_seg_display_val: out STD_LOGIC_VECTOR (6 downto 0) 	
	);
	end component;
	
	signal w_sys_rst: STD_LOGIC;
	
	signal w_count_sec0: STD_LOGIC_VECTOR (3 downto 0);
	signal w_count_sec1: STD_LOGIC_VECTOR (3 downto 0);
	signal w_count_min0: STD_LOGIC_VECTOR (3 downto 0);
	signal w_count_min1: STD_LOGIC_VECTOR (3 downto 0);
	
   signal w_time_clk: STD_LOGIC;
	signal w_sec0_carry_out: STD_LOGIC;
	signal w_sec1_carry_out: STD_LOGIC;
	signal w_min0_carry_out: STD_LOGIC;
	
	signal r_time_clk: STD_LOGIC;
	signal r_sec0_carry_out: STD_LOGIC;
	signal r_sec1_carry_out: STD_LOGIC;
	signal r_min0_carry_out: STD_LOGIC;

	signal w_sec0_carry_in: STD_LOGIC;
	signal w_sec1_carry_in: STD_LOGIC;
	signal w_min0_carry_in: STD_LOGIC;
	signal w_min1_carry_in: STD_LOGIC;
	
begin
	process(i_sys_rst,i_sys_clk)	
		begin
			if (i_sys_rst = '0') then	
				r_time_clk <= '0';
				r_sec0_carry_out <= '0';
				r_sec1_carry_out <= '0';
				r_min0_carry_out <= '0';
			elsif (i_sys_clk'event AND i_sys_clk = '1') then
				r_time_clk <= w_time_clk;
				r_sec0_carry_out <= w_sec0_carry_out;
				r_sec1_carry_out <= w_sec1_carry_out;
				r_min0_carry_out <= w_min0_carry_out;
			end if;	
	end process;
	w_sys_rst <= NOT i_sys_rst;
	w_sec0_carry_in <= w_time_clk AND (NOT r_time_clk);
	w_sec1_carry_in <= w_sec0_carry_out AND (NOT r_sec0_carry_out);
	w_min0_carry_in <= w_sec1_carry_out AND (NOT r_sec1_carry_out);
	w_min1_carry_in <= w_min0_carry_out AND (NOT r_min0_carry_out);
	U1: FREQUENCY_DIVIDER port map (	i_sys_clk => i_sys_clk, 
												i_sys_rst => w_sys_rst, 
											   o_div_clk => w_time_clk);
												
	U2: BCD_COUNTER generic map( mod_value => 9 
										)
						 port map  ( i_sys_clk => i_sys_clk,
										 i_sys_rst => w_sys_rst,
										 i_count_carry_in => w_sec0_carry_in,
										 o_count => w_count_sec0,
										 o_count_carry_out => w_sec0_carry_out
									   );	
	U3: BCD_COUNTER generic map( mod_value => 5 
										)
						 port map  ( i_sys_clk => i_sys_clk,
										 i_sys_rst => w_sys_rst,
										 i_count_carry_in => w_sec1_carry_in,
										 o_count => w_count_sec1,
										 o_count_carry_out => w_sec1_carry_out
									   );
	U4: BCD_COUNTER generic map( mod_value => 9 
										)
						 port map  ( i_sys_clk => i_sys_clk,
										 i_sys_rst => w_sys_rst,
										 i_count_carry_in => w_min0_carry_in,
										 o_count => w_count_min0,
										 o_count_carry_out => w_min0_carry_out
									   );	
	U5: BCD_COUNTER generic map( mod_value => 5 
										)
						 port map  ( i_sys_clk => i_sys_clk,
										 i_sys_rst => w_sys_rst,
										 i_count_carry_in => w_min1_carry_in,
										 o_count => w_count_min1,
										 o_count_carry_out => open
									   );										
										 
   U6: SEG_CONVERTER port map ( i_time_val => w_count_sec0,
											i_sys_rst => w_sys_rst,
											o_seg_display_val => o_sec0_display 
											);
										
	U7: SEG_CONVERTER port map ( i_time_val => w_count_sec1,
											i_sys_rst => w_sys_rst,
											o_seg_display_val => o_sec1_display 
											);
		
	U8: SEG_CONVERTER port map ( i_time_val => w_count_min0,
											i_sys_rst => w_sys_rst,
											o_seg_display_val => o_min0_display 
											);
										
	U9: SEG_CONVERTER port map ( i_time_val => w_count_min1,
											i_sys_rst => w_sys_rst,
											o_seg_display_val => o_min1_display 
											);									
	
end architecture behavior;
